1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a programmable redundancy circuit and more particularly, to a structure of a redundancy decoder (spare decoder).
2. Description of the Prior Art
Recently, in a high integrated memory device such as a dynamic MOS.RAM (Metal Oxide Semiconductor Random Access Memory), it has been desired to reduce power consumption with the development of high integration. In the dynamic MOS.RAM, a bit line charging and discharging current occupies a large amount of the total consumed current. Thus, recently, in each active cycle, only a memory cell array block related to an input address is operated and the other memory cell array blocks are not operated so that the bit line charging and discharging current of the bit line is reduced to half or three-fourths.
FIG. 1 is a block diagram showing a conventional example of, for example, a 1M-bit dynamic MOS.RAM comprising a block partitioned memory cell array.
The dynamic MOS.RAM shown in FIG. 1 is divided into four blocks #1 to #4. Each of the blocks #1 to #4 comprises two memory cell arrays 1a and 1b. The memory cell arrays 1a and 1b comprise spare rows 2a and 2b and spare columns 3a and 3b, respectively. Row sub-decoders 4 and row main decoders 5 are arranged on one side of each of the memory cell arrays 1a and 1b. Spare row sub-decoders 6a and 6b are arranged in respective one ends of the spare rows 2a and 2b. Four spare row main decoders 7 corresponding to the blocks #1 to #4 are arranged in the vicinity of the block #1. Each of the spare row main decoders 7 is connected to the spare row sub-decoders 6a and 6b in a corresponding one of the blocks #1 to #4 through a spare decoder selecting line L. A column decoder 9 is arranged between the memory cell arrays 2a and 2b in each of the blocks #1 to #4. A spare column decoder 10 is arranged between the spare columns 3a and 3b in each of the blocks #1 to #4.
In the dynamic MOS.RAM, any of the blocks #1 to #4 is selected by a combination of a row address signal RA.sub.8 and a row address signal RA.sub.9. In addition, either of the memory cell arrays 1a and 1b is selected by a column address signal CA.sub.9. For example, when RA.sub.8 equals 0, RA.sub.9 equals 0 and CA.sub.9 equals 0, the memory cell array 1a in the block #1 is selected. Row address signals RA.sub.0, RA.sub.0, . . . , RA.sub.9 and column address signals CA.sub.0, CA.sub.0, . . . , CA.sub.9, are generated from an address buffer circuit 30.
FIG. 2 is a diagram showing a structure of a memory cell array 1a and the peripheral portion included in any of blocks.
A memory cell array 1a comprises a plurality of word lines WL and a plurality of pairs of bit lines BL and BL intersecting with the word lines WL. The memory cell array 1a also comprises a plurality of memory cells MC each provided at an intersection of each of the word lines WL and one, BL or BL, of each of the bit line pairs. In addition, the memory cell 1a includes a spare row 2a comprising four spare word lines SWL and a spare column 3a comprising two spare bit line pairs SBL and SBL. A spare memory cell SMC is provided at an intersection of each of the spare word lines SWL and the bit line BL or BL or one, SBL or SBL, of each of the spare bit line pairs. The spare memory cell SMC is also provided between each of the word lines WL and the spare bit line SBL or SBL. A plurality of word lines WL are connected to row sub-decoders 5 in such a manner that each four word lines WL are connected to a corresponding sub-decoder 4. The row sub-decoders 5 are connected to row main decoders 4, respectively. Four word lines SWL are connected to a spare sub-decoder 6a. Selecting signals .PHI.W.sub.0 to .PHI.W.sub.3 are applied to the row sub-decoders 5 and the spare sub-decoder 6a from a selecting signal generating circuit 8. The bit line pairs BL and BL and the spare bit line pairs SBL and SBL which are in odd numbers are connected to a pair of input/output lines I/O.sub.0 and I/O.sub.0 through sense amplifiers SA and transistors Q1 and Q2. In addition, the bit line pairs BL and BL and the spare bit line pairs SBL and SBL which are in even numbers are connected to a pair of input/output lines I/O.sub.1 and I/O.sub.1 through sense amplifiers SA and transistors Q1 and Q2. Each of the transistors Q1 and Q2 corresponding to two adjacent bit line pairs BL and BL has a gate connected to a column decoder 9 through a column selecting line CL. Each of the transistors Q1 and Q2 corresponding to two adjacent spare bit line pairs SBL and SBL has a gate connected to a spare column decoder 10 through a spare column selecting line SCL. The pairs of input/output lines I/O.sub.0 and I/O.sub.0 and the pairs of input/output lines I/O.sub.1 and I/O.sub.1 are connected to an input/output circuit 20 through preamplifiers PA, respectively.
A memory cell array 1b, which is not shown in FIG. 2, and the memory cell array 1a are symmetric with respect to the column decoders 9.
Description is now made on operation of the memory cell array shown in FIG. 2. Any of the row main decoders 4 is selected in response to row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7. A row sub-decoder 5 connected to the selected row main decoder 4 is responsive to the selecting signals .PHI.W.sub.0 to .PHI.W.sub.3 for selecting any of the four word lines WL. Therefore, information stored in memory cells MC connected to the selected word line WL are read out to each of the bit lines BL and BL and amplified by a sense amplifier SA. Any of the column decoders 9 is then selected in response to address signals Y.sub.0 to Y.sub.15. The address signals Y.sub.0 to Y.sub.15 are formed based on column address signals CA.sub.1, CA.sub.1, . . . , CA.sub.7. The selected column decoder 9 outputs a column selecting signal to the column selecting line CL. Therefore, two pairs of transistors Q1 and Q2 connected to the column selecting line CL are turned on, so that information on two pairs of bit lines BL and BL are read out to the pair of input/output lines I/O.sub.0 and I/O.sub.0 and the pair of input/output lines I/O.sub.1 and I/O.sub.1, respectively, and amplified by preamplifiers PA. The input/output circuit 20 is responsive to column address signals CA.sub.0 and CA.sub.0 for reading out either of information on the pair of input/output lines I/O.sub.0 and I/O.sub.0 or the pair of input/output lines I/O.sub.1 and I/O.sub.1 to a data bus. The above described operation is performed in the same manner, in the memory cell arrays 1a and 1b.
Meanwhile, a defective memory cell may be formed in the manufacturing process. In this case, the spare row 2a is selected in place of a row including the defective memory cell. More specifically, when a row address signal for selecting the row including the defective memory cell is applied, not a corresponding row main decoder 4 but the spare row main decoder 7 (in FIG. 1) is selected. The spare row sub-decoder 6a connected to the spare row main decoder 7 is responsive to the selecting signals .PHI.W.sub.0 to .PHI.W.sub.3 for selecting any of the four spare word lines SWL.
On the other hand, if and when a defective memory cell is formed, not a column including the defective memory cell but the spare column 3a may be selected. More specifically, when a column address signal for selecting the column including the defective memory cell is applied, the spare column decoder 10 is selected in place of a corresponding column decoder 9.
FIG. 3 is a circuit diagram showing an example of structures of a row main decoder 4 and a row sub-decoder 5.
The row main decoder 4 comprises an AND gate 41 having a plurality of input terminals. Row address signals RA.sub.2 or RA.sub.2, . . . , RA.sub.7 or RA.sub.7 are applied to the input terminals of the AND circuit 41, respectively. The row sub-decoder 5 comprises four AND circuits 51 to 54. Each of the AND circuits 51 to 54 has one input terminal connected to an output terminal of the AND circuit 41. The AND circuits 51 to 54 have other input terminals receiving selecting signals .PHI.W.sub.1 to .PHI.W.sub.3 by a selecting signal generating circuit 8 as described below, respectively. The AND circuits 51 to 54 have output terminals connected to word lines WL, respectively.
When all of row address signals applied to the input terminals of the AND circuit 41 attain a high level (an "H" level), an output of the AND circuit 41 attains the "H" level. At that time, when any of the selecting signals .PHI.W.sub.0 to .PHI.W.sub.3 attains the "H" level, outputs of the AND circuits 51 to 54 receiving the selecting signals attain the "H" level. Therefore, one of the word lines WL is selected.
FIG. 4 is a circuit diagram showing an example of structures of a spare row main decoder 7 and a spare row sub-decoder 6a.
The spare row main decoder 7 comprises an address selector 71 and an AND circuit 72. The address selector 71 comprises a plurality of input terminals receiving row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7, RA.sub.7, and a plurality of output terminals outputting the row address signals RA.sub.2 or RA.sub.2, . . . , RA.sub.7 or RA.sub.7. The address selector 71 comprises a plurality of fuse-links. A row address signal provided to each of the output terminals is selected depending on whether or not the fuse-links are melted. The address selector 71 is set to output the same row address signal as that applied to a row main decoder 4 for selecting a row including a defective memory cell. The AND circuit 72 has input terminals receiving the row address signals outputted from the address selector 71. The AND circuit 72 has an output terminal connected to a spare decoder selecting line L. The spare row sub-decoder 6a comprises four AND circuits 61 to 64. Each of the AND circuits 61 to 64 has one input terminal connected to the spare decoder selecting line L. The AND circuits 61 to 64 have other input terminals receiving selecting signals .PHI.W.sub.0 to .PHI.W.sub.3 by a selecting signal generating circuit 8 as described below, respectively. Each of the AND circuits 61 to 64 has an output terminal connected to a spare word line SWL. The spare row sub-decoder 6a for a memory cell array 1a and a spare row sub-decoder 6b for a memory cell array 1b are connected to a single spare row main decoder 7 through the spare decoder selecting line L. In FIG. 4, only the spare row sub-decoder 6a is illustrated.
When all of the row address signals applied to the input terminals of the AND circuit 72 attain the "H" level, an output of the AND circuit 22 attains the "H" level. At that time, when any of the selecting signals .PHI.W.sub.0 to .PHI.W.sub.3 attains the "H" level, outputs of the AND circuits 61 to 64 receiving the selecting signals attain the "H" level, whereby only one of the spare word lines SWL is selected.
FIG. 5 is a circuit diagram showing an example of a structure of a selecting signal generating circuit 8.
The selecting signal generating circuit 8 comprises four AND circuits 81 to 84 each having three inputs and four AND circuits 85 to 88 each having two inputs. Each of the AND circuits 81 to 84 has an input terminal receiving a row address signal RA.sub.0 or RA.sub.0, and other input terminal receiving a row address signal RA.sub.1 or RA.sub.1. Each of the AND circuits 81 to 84 has remaining one input terminal receiving a row address signal RA.sub.8 or RA.sub.8 common. The row address signal RA.sub.8 is applied in the selecting signal generating circuit 8 in blocks #2 and #4, and the row address signal RA.sub.8 is applied in the selecting signal generating circuit 8 in blocks #1 and #3. Each of the AND circuits 85 to 88 has one input terminal receiving an output signal of each of the AND circuits 81 to 84 and other input terminal receiving a word line driving signal .PHI.W in common. Selecting signals .PHI.W.sub.0 to .PHI.W.sub.3 are derived from output terminals of the AND circuits 85 to 88, respectively.
Any of outputs of the AND circuits 81 to 84 attains an "H" level in response to the levels of the row address signals RA.sub.0, RA.sub.0, RA.sub.1, RA.sub.1 and RA.sub.8. When the word line driving signal .PHI.W attains the "H" level, any of the selecting signals .PHI.W.sub.0 to .PHI.W.sub.3 attains the "H" level.
FIG. 6 is a circuit diagram showing an example of a structure of a column decoder 9.
The column decoder 9 comprises an AND circuit 91 having four inputs. The AND circuit 91 has one input terminal receiving any of address signals Y.sub.0, Y.sub.1, Y.sub.2 and Y.sub.3, other input terminal receiving any of address signals Y.sub.4, Y.sub.5, Y.sub.6 and Y.sub.7, other input terminal receiving any of address signals Y.sub.8, Y.sub.9, Y.sub.10 and Y.sub.11, and remaining one input terminal receiving any of address signals Y.sub.12, Y.sub.13, Y.sub.14 and Y.sub.15. The address signals Y.sub.0 to Y.sub.15 are obtained by decoding column address signals CA.sub.1, CA.sub.1, . . . , CA.sub.8. The AND circuit 91 has an output terminal connected to a column selecting signal line CL. In the column decoder 9, when all of the address signals applied to the input terminals of the AND circuit 91 attain an "H" level, a column selecting signal at a high level is provided to the column selecting signal line CL.
FIG. 7 is a circuit diagram showing an example of a structure of a spare column decoder 10.
The spare column decoder 10 comprises a fuse latch 11, four address selectors 12 and an AND circuit 13. Each of the address selectors 12 has four input terminals receiving address signals and one output terminal, and derives from the output terminal any of the address signals applied to the input terminals. Address signals Y.sub.0 to Y.sub.3, Y.sub.4 to Y.sub.7, Y.sub.8 to Y.sub.11 and Y.sub.12 to Y.sub.15 are applied to the four address selectors 12, respectively. The AND circuit 13 has an input terminal receiving outputs of the fuse latch 11 and the four address selectors 12. The AND circuit 13 has an output terminal connected to a spare column selecting line SCL. Each of the address selectors 12 is set to output the same address signal as that applied to a column decoder 9 for selecting a column including a defective memory cell. In the spare column decoder 10, when the output of the fuse latch 11 attains an "H" level and all of the outputs of the four address selectors 12 attain the "H" level, a column selecting signal at a high level is provided to the spare column selecting line SCL.
FIG. 8 is a circuit diagram showing an example of a structure of the fuse latch 11 shown in FIG. 7.
The fuse latch 11 comprises a resistor R, a fuse-link FS, N channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) Q11 and Q12 and a P channel MOSFET Q13. FIG. 8, the fuse-link FS is connected between a node N1 and a power supply terminal and the resistor R is connected between the node N1 and a ground terminal. In addition, the MOSFET Q11 is connected between the node N1 and the ground terminal. The MOSFET Q11 has a gate connected to a node N2. The MOSFET Q13 is connected between the power supply terminal and the node N2. The MOSFET Q13 has a gate connected to the node N1. The MOSFET Q12 is connected between the node N2 and the ground terminal. The MOSFET Q12 has a gate connected to the node N1.
In the fuse latch 11, since the resistance value of the fuse-link FS is lower than that of the resistor R when the fuse-link FS is not melted, a potential of the node N1 attains a high level, so that an output at a low level is derived from the node N2. When the fuse-link FS is melted by a laser or the like, the potential of the node N1 attains a low level, so that an output at a high level is derived from the node N2. The MOSFET Q11 prevents the node N1 from floating when the fuse-link FS is melted.
FIG. 9 is a circuit diagram showing an example of a structure of one of the address selectors 12 shown in FIG. 7.
Referring to FIG. 9, P channel MOSFETs Q21 and Q22 connected in series and N channel MOSFETs Q23 and Q24 connected in series are connected in parallel with each other between an input terminal Il and an output terminal O1. In the same manner, P channel MOSFETs Q25 and Q26 and N channel MOSFETs Q27 and Q28 are connected to each other between an input terminal I2 and the output terminal O1. In the same manner, P channel MOSFETs Q29 and Q30 and N channel MOSFETs Q31 and Q32 are connected to each other between an input terminal I3 and the output terminal 01. In the same manner, P channel MOSFETs Q33 and Q34 and N channel MOSFETs Q35 and Q36 are connected to each other between an input terminal I4 and the output terminal O1. Each of the MOSFETs Q23, Q25, Q31 and Q33 has a gate receiving an output signal from a fuse latch 14. Each of the MOSFETs Q21, Q27, Q29, and Q35 has a gate receiving an output signal of an inverter 16 for inverting the output signal from the fuse latch 14. Each of the MOSFETs Q24, Q28, Q30 and Q34 has a gate receiving an output signal from a fuse latch 15. Each of the MOSFETs Q22, Q26, Q32 and Q36 has a gate receiving an output signal of an inverter 17 for inverting the output signal from the fuse latch 15. The structures of the fuse latches 14 and 15 are the same as that of the fuse latch 11 shown in FIG. 8. More specifically, when a fuse-link contained in each of the fuse latches 14 and 15 is not melted, the output signal of the fuse latch attains an "L" level. On the other hand, when the fuse-link is melted, the output signal thereof attains an "H" level.
When both of the fuse-links in the fuse latches 14 and 15 are being melted, the MOSFETs Q21, Q22, Q23, Q24, Q26, Q28, Q29 and Q31 are rendered conductive, so that an address signal Y.sub.4i (i=0, 1, 2, 3) applied to the input terminal I1 is transmitted to the output terminal O1. In the same manner, when only the fuse-link in the fuse latch 15 is melted, an address signal Y.sub.4i+1 applied to the input terminal I2 is transmitted. When only the fuse-link in the fuse latch 14 is melted, an address signal Y.sub.4i+2 applied to the input terminal I3 is transmitted. When neither of the fuse-links in the fuse latches 14 and 15 is melted, an address signal Y.sub.4i+3 applied to the input terminal I4 is transmitted.
In the above described conventional dynamic MOS.RAM, since the spare row main decoder 7 is larger, by the size of the address selector 71, than the nominal row main decoder 4 (see FIGS. 3 and 4), the spare row main decoder 7 is arranged in the peripheral circuit portion in many cases, as shown in FIG. 1. In this case, spare decoder selecting lines L connected between the spare row main decoder 7 and the spare row sub-decoders 6a and 6b are required, the number of which is the same as that of the spare row main decoders 7. Since the spare decoder selecting lines L are arranged at the side of the memory cell arrays 1a and 1b, the chip size is increased when the number of spare decoders is increased.
Furthermore, in the above described conventional dynamic MOS.RAM, since an address selector included in a spare decoder comprises a number of fuse-links and transfer gates which are disadvantageous for the pattern layout (see FIG. 9), the chip size is increased when the number of spare decoders is increased.
Examples of a circuit of a redundancy decoder and a circuit for replacing a defective memory cell with a spare memory cell are described in an article "REDUNDANCY", Electronics, July 28, 1981, pp. 116-134, an article "Laser Programmable Redundancy and Yield Improvement in a 64K DRAM", IEEE Journal of Solid State Circuits, Vol. SC-16, October, 1981, pp. 506-513, and an article "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", IEEE Journal of Solid State Circuits, Vol. SC-16, October, 1981, pp. 435-443.